1. Field
This disclosure relates generally to data recovery and, more specifically, to techniques for asynchronous data recovery.
2. Related Art
Existing approaches for performing asynchronous data recovery have employed high-speed asynchronous interfaces (e.g., digital radio frequency third generation (DigRF3G), serializer/deserializer (SerDes), universal serial bus (USB) interfaces) that have utilized multiple phases of an internal clock to over-sample preamble bits of a data frame. Typically, based on a correlation phase selection algorithm, the interfaces have selected one of the clock phases to facilitate sampling of data bits in a data frame. In general, the approaches have required the generation of relatively accurate distributed clock phases, which may be provided by relatively simple digital dividers or relatively complex delay lock loops (DLLs). Unfortunately, in an interface that employs multiple clock phases, the effects of phase imbalance on performance of the interface is usually difficult to quantify.
Moreover, the design of high-speed asynchronous interfaces has become increasingly complex as bit rates of transmitted data has increased. For example, the design of digital radio frequency fourth generation (DigRF4G) interfaces (which may have bit rates greater than 2 gigabits/second) and SerDes interfaces (which may have bit rates greater than 1 gigabits/second) has been relatively complex. Furthermore, interfaces that employ multiple phase generation have relatively high power consumption, as the interfaces toggle at a rate that is at least twice the data rate, irrespective of a data duty cycle. Additionally, for interfaces that employ DLLs, power consumption is usually relatively high even after a phase is selected, as conventional high-speed asynchronous interfaces have usually continued to generate unwanted phases. In addition, as the interfaces have employed a sampling mechanism that is highly dependent on phase relationship, data frame size is also usually limited.